+91 87884 14717   

ME/M.Tech Projects


  • Hardware realization of sensors interfacing with FPGA
  • Design for Low Power Multiplier Based On Fixed Width Replica Redundancy Block & Compressor Trees
  • Design and Implementation of 8-Bit Vedic Multiplier
  • Sensors Interfacing on Re-configurable Platform using FPGA in IoT environment
  • A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier Design
  • IoT Based Health Monitoring Using FPGA
  • A Novel Design for High Speed Multiplier for Digital Signal Processing Applications
  • Implementation of Floating Point Multiplier Using Dadda Algorithm
  • Implementation Of Signed Vedic Multiplier Targeted At FPGA Architectures
  • FPGA Implementation Of High Performance Multiplier Using Squarer